1. Field of the Invention
The present invention generally relates to the field of semiconductor structures. More particularly, the invention relates to transistor semiconductor structures.
2. Background Art
By utilizing BiFET technology, bipolar transistors, such as heterojunction bipolar transistors (HBTs), and field effect transistors (FETs), such as enhancement-mode (E-mode) and depletion-mode (D-mode) FETs, can be integrated on the same semiconductor die to provide increased circuit design flexibility. In an integrated structure, a bipolar transistor, such as an HBT, an E-mode FET, and a D-mode FET can each be advantageously tailored for specific applications. For example, an HBT, a D-mode FET, and an E-mode FET can be integrated on a substrate, such as a semi-insulating gallium arsenide (GaAs) substrate, to form a power amplifier, a bias circuit, and a radio frequency (RF) switch, respectively, for a communications device, such as a cell phone. However, previous attempts at integrating a bipolar transistor with E-mode and D-mode FETs on a substrate have undesirably affected the respective performances of the E-mode and D-mode FETs.
In one conventional approach, for example, an HBT can be formed over a substrate, such as a semi-insulating GaAs substrate, and E-mode and D-mode FETs can be integrated under the sub-collector of the HBT. However, in this conventional approach, the E-mode and D-mode FETs typically have shared epitaxial layers, which can undesirably affect the analog properties of the E-mode FET. Also, as a result of the shared epitaxial layers, coupling can occur between the E-mode and D-mode FETs, which can undesirably affect the RF switching performance of the D-mode FET. Thus, in the aforementioned conventional approach, the performance of the E-mode FET cannot be optimized without affecting the performance of the D-mode FET, and vice versa.